High resistance silicon substrates are used in analog and mixed signal technologies to reduce parasitic coupling and capacitance to substrate. Examples of devices that benefit from high resistance silicon include inductors (reduced eddy current losses in substrate), NPN transistors (reduced collector capacitance to substrate), and switch FET's (reduced parasitic capacitance to substrate, reduced high frequency rf harmonics losses to substrate).
The final resistivity of silicon is a function of several factors including, e.g.: (i) starting resistivity; (ii) oxygen content (e.g., oxygen turns into a n-type dopant with back end of the line (BEOL) process temperatures, e.g., low temperatures of about 400° C., and can type-convert a p-type substrate to n-type); and (iii) thermal history. In high resistance silicon substrate technologies the final substrate resistivity is specified within a predetermine range. Examples of final resistivity specifications include 1000+/−200Ω−cm p-type, 3000+/−1000Ω−cm p-type, 10,000+/−2000Ω−cm p-type, and 1000+/−300Ω−cm n-type. In general, as the substrate resistivity increases, the depletion region surrounding devices such as NPN collectors also increases and, if the substrate resistivity is out of specification on the high side or the p-type substrate type converts to n-type, then the depletion regions between two adjacent devices can merge or, in the case of type-conversion, the two devices can be shorted through the substrate. This merging or shorting results in high leakage currents and device failure. The formation of these depletion regions is also affected by operating temperature. In addition, if the resistivity flips from p-type to n-type, due to type conversion of oxygen to n-type dopants, all active and passive devices in the wafer effectively will be shorted together. Accordingly, in current process flows, active devices such as NPN transistors, CMOS transistors, and other active or passive devices are designed specified distances apart to avoid punch-through between collectors. The distance between these devices is calculated based on the final silicon resistivity specification and the maximum applied voltage, i.e., devices in a 10,000Ω−cm final resistivity substrate would be spaced further apart than devices in a 1000Ω−cm final resistivity substrate.